Cadence Says AI Agents Are Compressing Chip Design Timelines, and India Could Build the Next Semiconductor Startup Wave

The bottleneck in building a chip has never really been silicon. It has been engineers — the scarce, expensive, slow-to-train humans who write the register-transfer logic, grind through verification regressions and sign off on a layout before a mask set costs somebody nine figures. Cadence Design Systems, whose software most of the world’s chip designers effectively live inside, now says that constraint is finally breaking. And it is arguing that the country best positioned to exploit the break is India.

In an interview with The Economic Times published August 18, Paul Cunningham, senior vice president and general manager of Cadence’s System Verification Group, said AI is increasingly automating semiconductor design and verification, and that India could build a semiconductor startup ecosystem comparable to the United States within a decade. Cadence has assigned hundreds of employees to AI agents spanning chip design, verification, physical implementation and packaging, Cunningham said. Roughly a third of the company’s global workforce is based in India — about 4,200 people, per Business Standard — making it Cadence’s largest engineering base outside the US.

The commercial case is already showing up in the financials. In the second quarter, reported July 27, Cadence posted revenue of $1.584 billion, up from $1.275 billion a year earlier. Core EDA — the traditional chip design tools business — grew 18% year over year, which the company attributed to demand for its AI portfolio and expanded adoption across hyperscalers, top semiconductor firms and startups. Backlog hit a record $8.1 billion. Cadence raised its full-year 2026 outlook to 19% revenue growth, non-GAAP EPS of $8.10 and $2 billion in operating cash flow.

“Cadence delivered an outstanding Q2 driven by broad-based strength and the accelerating demand for our AI-driven solutions across both Design for AI and AI for Design fronts,” chief executive Anirudh Devgan said in the results release. He added that Cadence is “uniquely positioned to capitalize on this massive TAM expansion opportunity as the only provider with agentic solutions spanning the full electronic system design flow.”

The agents, and what they actually do

Cadence’s agentic push is not vaporware. ChipStack, launched in February and pitched as the industry’s first fully autonomous virtual design and verification AI agent, was extended to what the company calls Level-5 autonomy at COMPUTEX 2026 through a collaboration with NVIDIA using Nemotron models. A joint demo showed more than 40x faster RTL validation, collapsing a typical five-week verification cycle to under a day. Cadence says ChipStack has picked up more than 20 customer engagements. In one deployment on a PCIe 7 controller, the agent autonomously generated substantial portions of the design and verification environment and delivered roughly a 2x schedule improvement.

Around it sits a widening portfolio: ViraStack, InnoStack, and AuraStack, launched during Q2 for advanced packaging and PCB. That last piece matters — packaging is where chiplet-era complexity is concentrating, and Cadence’s System Design and Analysis segment grew 37% year over year.

The motivation Cunningham offers is less about cost-cutting than arithmetic. Cadence estimates the industry will face a shortfall of hundreds of thousands of design and verification engineers by the end of the decade.

“The future will be a world where the productivity is another 10X compared to today,” Cunningham told EE Times Asia in June. “If we don’t have agents, then we would need to hire 10 times the people because the semiconductor industry is growing so fast and the complexity is growing so fast.”

Why it matters: AI is now designing the chips that run AI

Strip away the vendor framing and there is a genuinely recursive story here. The compute buildout driving AI demand requires accelerators, memory controllers, interconnects and packaging designed at a pace human teams cannot sustain. The tools compressing those schedules are themselves LLM-driven agents running on the previous generation of that silicon. Cadence has a name for both halves — “Design for AI” and “AI for Design” — and that a single vendor now books both as growth lines is the clearest evidence yet that the loop is closing commercially, not just rhetorically.

It is worth being precise about what has not changed. Cunningham is emphatic that agents do not replace sign-off. “The agent always needs to check with our proven engineering-based software that it is correct and safe,” he said. “We will not change the signature. We will just make it more efficient to get to the point where we can sign.” Nor does he think general-purpose assistants will do this work: “I actually think that a super agent for chip design is almost like another EDA tool.” Inference economics also bite — Cunningham notes that “tokens are very expensive,” pushing Cadence toward a multi-model strategy.

The India claim follows from all of this. If agents compress the headcount and calendar required to get from specification to tapeout, the barrier to founding a fabless chip company drops toward something closer to a software startup’s. India has the design talent density and, increasingly, the policy scaffolding: the India Semiconductor Mission is now a roughly Rs 1.27 lakh crore commitment, the Design Linked Incentive scheme has backed 24 design startups that have raised about Rs 430 crore in venture funding, and design infrastructure support has reached 315 academic institutions and 104 startups as of May 2026. The government has signalled it wants at least 50 fabless companies enabled in the next phase.

What it does not yet have is a track record of Indian-founded chip companies reaching scale, and no amount of agentic tooling substitutes for the fab access, IP libraries and patient capital that take a design to volume.

Three things to watch. First, Cadence’s Q3 results in late October, and whether core EDA growth holds at the high-teens rate AI demand produced this quarter — the cleanest proxy for whether agentic EDA is expanding the market or merely repricing it. Second, whether the 20-plus ChipStack engagements convert into recurring seats rather than pilots. Third, and most consequential for the India thesis: first silicon from the Tata-PSMC fab at Dholera, targeted for December 2026. A design ecosystem needs somewhere to send its tapeouts.